Compatible Systems RISC 2800i Instrukcja Użytkownika Pobierz pdf (Strona 39)

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4

Freescale Semiconductor 39

System Design Information

Figure 17. MPC7448 Power Down Sequencing Requirements

There is no requirement regarding AV

during power down, but it is recommended that AV

track V

within the RC time constant of the PLL filter circuit described in Section 9.2.2, “PLL Power Supply

Filtering” (nominally 100 µs).

9.2.2 PLL Power Supply Filtering

The AV

power signal is provided on the MPC7448 to provide power to the clock generation PLL. To

ensure stability of the internal clock, the power supplied to the AV

input signal should be filtered of any

noise in the 500-KHz to 10-MHz resonant frequency range of the PLL. The circuit shown in Figure 18

using surface mount capacitors with minimum effective series inductance (ESL) is strongly recommended.

In addition to filtering noise from the AV

input, it also provides the required delay between V

and

as described in Section 9.2.1, “Power Supply Sequencing.”

The circuit should be placed as close as possible to the AV

pin to minimize noise coupled from nearby

circuits. It is often possible to route directly from the capacitors to the AV

pin, which is on the periphery

of the device footprint.

Figure 18. PLL Power Supply Filter Circuit

no restrictions between V

and OV

SYSCLK

0.9 V

no restrictions between V

and AV

note also restrictions between SYSCLK and OV

0.9 V

limit imposed by V

if V

ramps down first

limit imposed by OV

if OV

ramps down first

10 Ω

2.2 µF 2.2 µF

GND

Low ESL Surface Mount Capacitors

1 2 ... 34 35 36 37 38 39 40 41 42 43 44 ... 59 60

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Compatible Systems RISC 2800i Instrukcja Użytkownika Strona 39

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